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Victor Mignot a22e0a7738
Add first basic implementation of a RISC-V hart. 
This commit add the main components to run a simple RISC-V hart.
This hart implement all the RV32I instructions (excepted FENCE and
System instruction ones).
Multicore is not implemented as it would need first to implement the
RISC-V Weak Memory Ordering model into our harts.
2024-05-10 15:22:44 +02:00
src Add first basic implementation of a RISC-V hart. 2024-05-10 15:22:44 +02:00
.gitignore Initial structure and files 2024-03-22 17:15:23 +01:00
Cargo.lock Initial structure and files 2024-03-22 17:15:23 +01:00
Cargo.toml Initial structure and files 2024-03-22 17:15:23 +01:00
flake.lock Initial structure and files 2024-03-22 17:15:23 +01:00
flake.nix Initial structure and files 2024-03-22 17:15:23 +01:00
LICENSE Initial structure and files 2024-03-22 17:15:23 +01:00
README.md Initial structure and files 2024-03-22 17:15:23 +01:00

README.md

dremu

A RISC-V 32-bits CPU emulator.

License

Licensed under the European Union Public Licence (EUPL).

Copyright (c) 2024 Victor Mignot