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Victor Mignot 78852a7cc6
Initial structure and files
2024-03-22 17:15:23 +01:00
src Initial structure and files 2024-03-22 17:15:23 +01:00
.gitignore Initial structure and files 2024-03-22 17:15:23 +01:00
Cargo.lock Initial structure and files 2024-03-22 17:15:23 +01:00
Cargo.toml Initial structure and files 2024-03-22 17:15:23 +01:00
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README.md Initial structure and files 2024-03-22 17:15:23 +01:00

README.md

dremu

A RISC-V 32-bits CPU emulator.

License

Licensed under the European Union Public Licence (EUPL).

Copyright (c) 2024 Victor Mignot