a22e0a7738
This commit add the main components to run a simple RISC-V hart. This hart implement all the RV32I instructions (excepted FENCE and System instruction ones). Multicore is not implemented as it would need first to implement the RISC-V Weak Memory Ordering model into our harts.
115 lines
4.6 KiB
Rust
115 lines
4.6 KiB
Rust
//! The RV32I Store instructions.
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//! These instructions allow to write data on the system bus.
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//! All these instructions use the same opcode and use the S-type instruction format.
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use crate::core::isa::{Instruction, RVException, RVHart};
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/// The Store instructions opcode.
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pub const STORE_OPCODE: u32 = 0x23;
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/// The start bit for the `rs1` field on the 32-bits encoded instruction.
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const RS1_START_BIT: usize = 15;
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/// The start bit for the `rs2` field on the 32-bits encoded instruction.
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const RS2_START_BIT: usize = 20;
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/// The start bit for the `funct3` field on the 32-bits encoded instruction.
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const FUNCT3_START_BIT: usize = 12;
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/// The start bit for the `imm[4:0]` field on the 32-bits encoded instruction.
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const IMM_4_0_START_BIT: usize = 7;
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/// The start bit for the `imm[11:5]` field on the 32-bits encoded instruction.
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const IMM_11_5_START_BIT: usize = 25;
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/// The mask to apply on top of the encoded instruction shifted to `FUNCT3_START_BIT` to extract the `funct3` value.
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const FUNCT3_MASK: u32 = 0b111;
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/// The mask to apply on top of the encoded instruction shifted to a register field to extract the register index value.
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const REGISTER_INDEX_MASK: u32 = 0x1f;
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/// The mask to apply on top of the encoded instruction shifted to `IMM_4_0_START_BIT` to extract the `imm[4:0]` value.
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const IMM_4_0_MASK: u32 = 0x1f;
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/// The `funct3` field code for the SB operation.
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const FUNCT3_SB_CODE: u32 = 0b000;
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/// The `funct3` field code for the SH operation.
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const FUNCT3_SH_CODE: u32 = 0b001;
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/// The `funct3` field code for the SW operation.
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const FUNCT3_SW_CODE: u32 = 0b010;
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/// All the available Store instruction.
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enum StoreOperation {
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/// Store Byte
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/// Store the `rs2` 8 least significant bits at the address resulting from the addition of the `rs1` register and the signed-extended 12-bits immediate.
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SB,
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/// Store Halfword
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/// Store the `rs2` 16 least significant bits at the address resulting from the addition of the `rs1` register and the signed-extended 12-bits immediate.
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SH,
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/// Store Word
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/// Store the `rs2` register value at the address resulting from the addition of the `rs1` register and the signed-extended 12-bits immediate.
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SW,
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/// Unknown operation.
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/// This is the result of having a `funct3` instruction field that does not match any of the previous operations.
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Unknown,
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}
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/// A decoded Store instruction, ready to be executed.
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pub struct StoreInstruction {
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/// The hart's X register index holding the base address to which should be added the signed immediate to get the effective address where data should be written.
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rs1: usize,
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/// The hart's X register index holding the data to be stored at the given address.
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rs2: usize,
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/// The store operation to be applied.
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funct3: StoreOperation,
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/// The sign-extended 12-bits immediate that should be added to the `rs1` register value to get the store effective address.
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imm: u32,
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}
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impl StoreInstruction {
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/// Decode the given raw `instruction` into a new `StoreInstruction` ready to be executed.
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pub fn new(instruction: u32) -> Self {
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let rs1 = ((instruction >> RS1_START_BIT) & REGISTER_INDEX_MASK) as usize;
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let rs2 = ((instruction >> RS2_START_BIT) & REGISTER_INDEX_MASK) as usize;
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let funct3 = match (instruction >> FUNCT3_START_BIT) & FUNCT3_MASK {
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FUNCT3_SB_CODE => StoreOperation::SB,
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FUNCT3_SH_CODE => StoreOperation::SH,
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FUNCT3_SW_CODE => StoreOperation::SW,
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_ => StoreOperation::Unknown,
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};
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let imm_4_0 = (instruction >> IMM_4_0_START_BIT) & IMM_4_0_MASK;
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let imm_11_5 = (instruction as i32 >> IMM_11_5_START_BIT) as u32;
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let imm = (imm_11_5 << 5) | imm_4_0;
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StoreInstruction {
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rs1,
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rs2,
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funct3,
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imm,
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}
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}
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}
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impl Instruction for StoreInstruction {
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fn execute(&self, core: &mut RVHart) -> Result<(), RVException> {
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let dest = (core.x[self.rs1] as i32).wrapping_add(self.imm as i32) as u32;
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match self.funct3 {
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StoreOperation::SB => {
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core.store_byte(dest, core.x[self.rs2] as u8);
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Ok(())
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}
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StoreOperation::SH => {
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core.store_halfword(dest, core.x[self.rs2] as u16);
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Ok(())
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}
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StoreOperation::SW => {
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core.store_word(dest, core.x[self.rs2]);
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Ok(())
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}
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StoreOperation::Unknown => Err(RVException::InstructionDecodeError),
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}
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}
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}
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#[cfg(test)]
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mod test {
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// TODO: Add test when proper bus and memory unit implementation.
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}
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