dremu

3 commits 1 branch 0 tags 65 KiB

Author	SHA1	Message	Date
Victor Mignot	a22e0a7738	Add first basic implementation of a RISC-V hart. This commit add the main components to run a simple RISC-V hart. This hart implement all the RV32I instructions (excepted FENCE and System instruction ones). Multicore is not implemented as it would need first to implement the RISC-V Weak Memory Ordering model into our harts.	2024-05-10 15:22:44 +02:00
Victor Mignot	f28056da82	Implement AddressSpace Add the first implementation to represent an address space (through the `AddressSpace` struct), that can be used by different objects which have their own inner memory map. The implementation use an AVLTree (right now it's just an ordinary BST, as rebalancing has not been implemented).	2024-05-10 14:53:16 +02:00
Victor Mignot	78852a7cc6	Initial structure and files	2024-03-22 17:15:23 +01:00

Author

SHA1

Message

Date

Victor Mignot

a22e0a7738

Add first basic implementation of a RISC-V hart.

This commit add the main components to run a simple RISC-V hart.
This hart implement all the RV32I instructions (excepted FENCE and
System instruction ones).
Multicore is not implemented as it would need first to implement the
RISC-V Weak Memory Ordering model into our harts.

2024-05-10 15:22:44 +02:00

Victor Mignot

f28056da82

Implement AddressSpace

Add the first implementation to represent an address space (through the
`AddressSpace` struct), that can be used by different objects which have
their own inner memory map.
The implementation use an AVLTree (right now it's just an ordinary BST,
as rebalancing has not been implemented).

2024-05-10 14:53:16 +02:00

Victor Mignot

78852a7cc6

Initial structure and files

2024-03-22 17:15:23 +01:00